`include "../../src/ImmGen.v"
`timescale 1ps/1ps

module testbench;
    reg[31:0] in;
    initial in = 32'h0000;

    wire[63:0] out;

    initial
    begin
        in = 32'h0000;
        #10 in = 32'h0001;
        #10 in = 32'h0002;
        #10 in = 32'h0003;
        #10 in = 32'h0004;
        #10 in = 32'h0005;
        #10 in = 32'h0006;
        #10 $stop;
    end

    ImmGen U0(in, out);

    initial
    begin
        $dumpfile("test.lxt");
        $dumpvars;
    end


endmodule